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upi semiconductor corp., http://www.upi-semi.com rev. f01, file name: up6111a/b-ds-f0101 up6111a/b 1 single phase pwm controller for mobile applications wide input voltage range 2v ~ 26v wide output voltage range 0.75v ~ 5.5v 1.0% initial accuracy constant on time pwm quasi constant switching frequency adjustable frequency from 200khz to 500khz ultra fast transient response integrated bootstrap diode integrated mosfet drivers with shoot-through protection configurable forced continuous current mode or power saving mode lossless, programmable overcurrent protection use low-side mosfet r ds(on) internal soft start over voltage and under voltage protection power ok indication wqfn4x4 - 16l, wqfn3x3 - 16l, vqfn3.5x3.5 - 14l, or tssop - 14l packages rohs compliant and 100% lead free r e b m u n r e d r oe p y t e g a k c a pk r a m e r d e q a 1 1 1 6 p ul 6 1 - 4 x 4 n f q w d n a x a m i o t r e f e r tn on o i t p i r c s e d n i p . 5 . p n o d d q a 1 1 1 6 p ul 6 1 - 3 x 3 n f q w c h q b 1 1 1 6 p ul 4 1 - 5 . 3 x 5 . 3 n f q v c a t b 1 1 1 6 p ul 4 1 - p o s s t power supplies for microprocessors or subsystem power supplies cable modems, set top boxes, and dsl modems industrial power supplies; general purpose supplies 2v to 26v input dc-dc regulators low-voltage distributed power supplies general description a pplications ordering information features the up6111a/b is a high performance synchronous-rectified buck controller specifically designed for pol voltage regulation in notebook pc application. the controller operates with 5v bias voltage and converts 2v~26v input voltage to 0.75v~5.5v output voltage. the up6111a/b adopts constant-on-time pwm scheme that features easy-to-use, low external component count, fast transient response and quasi constant frequency operation over the operation range. selectable forced continuous conduction mode (fccm) or power saving mode (psm) enables the flexibility for low noise operation or high efficiency conversion over wide output current range. lossless current sensing by r ds(on) of lower switch achieves programmable over current protection. other features include internal soft start, integrated bootstrap diode and thermal shutdown. the up6111a is available in wqfn3x3 -16l and wqfn4x4-16l packages. the up6111b is available in vqfn3.5x3.5- 14l and tssop- 14l packages. note: upi products are compatible with the current ipc/ jedec j-std-020 requirement. they are halogen-free, rohs compliant and 100% matte tin (sn) plating that are suitable for use in snpb or pb-free soldering processes.
upi semiconductor corp., http://www.upi-semi.com rev. f01, file name: up6111a/b-ds-f0101 up6111a/b 2 pin configuration typical application circuit 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 ugate phase imax pvcc lgate pgnd agnd nc vout vcc fb pok ton en/psm nc boot wqfn 3x3 or 4x4 C 16l up6111a agnd en/psm boot ton vout vcc 1 2 3 411 12 13 14 fb 5 pok 6 agnd 7 10 9 8 ugate phase imax pvcc lgate pgnd tssop-14 up6111b 1 14 13 12 11 10 2 3 4 5 7 8 ton vout vcc fb pgnd agnd ugate phase pvcc lgate boot en/psm vqfn 3.5x3.5-14l up6111b 6 9 pok imax agnd pgnd pvcc ton phase lgate v in vcc agnd ugate boot pok imax en/psm fb vout v out 5vcc phase pgnd pvcc ton phase lgate v in vcc agnd ugate boot pok imax en/psm fb vout v out up6111a up6111b 5vcc r1 r2 r1 r2
upi semiconductor corp., http://www.upi-semi.com rev. f01, file name: up6111a/b-ds-f0101 up6111a/b 3 functional block diagram up6111a pvcc lgate phase ugate boot soft start gate control logic on time calculation 1 shot por & reference pvcc pgnd fb ton vcc imax fault logic pok diode emulator en/psm vout agnd 70%v ref 90%v ref 115%v ref uvp pok ovp ocp 0.75v v ref 1.0v phase 20ua min off time
upi semiconductor corp., http://www.upi-semi.com rev. f01, file name: up6111a/b-ds-f0101 up6111a/b 4 up6111b functional block diagram pvcc lgate phase ugate boot soft start gate control logic on time calculation 1 shot por & reference pvcc pgnd fb ton vcc imax fault logic pok diode emulator en/psm vout agnd 70%v ref 90%v ref 115%v ref uvp pok ovp ocp ucp 0.75v v ref 1.0v phase 10ua min off time
upi semiconductor corp., http://www.upi-semi.com rev. f01, file name: up6111a/b-ds-f0101 up6111a/b 5 functional pin descriptio n e m a n n i pn o i t c n u f n i p t u o v . n o i t c e t e d e g a t l o v t u p t u o e g a t l o v t u p t u o r o f e g a t l o v t u p t u o r e t r e v n o c e h t o t y l t c e r i d n i p s i h t t c e n n o c . g n i s n e s c c v . c i e h t r o f e g a t l o v y l p p u s e g a t l o v v 5 o t n i p s i h t t c e n n o c . c i e h t r o f e g a t l o v s a i b s e d i v o r p n i p s i h t . r e t l i f c / r a h t i w t i s s a p y b d n a e c r u o s b f . r e t r e v n o c k c u b r o f e g a t l o v k c a b d e e f r o t s i s e r a . r e i f i l p m a r o r r e e h t o t t u p n i g n i t r e v n i e h t s i n i p s i h t . e g a t l o v n o i t a l u g e r e h t t e s o t d e s u s i d n g o t t u p t u o e h t m o r f r e d i v i d k o p . n o i t a c i d n i k o e g a t l o v t u p t u o t i . s u t a t s e g a t l o v t u p t u o g n i t a c i d n i r o f t u p t u o n i a r d n e p o n a s i n i p s i h t . r u c c o s t l u a f o n d n a n o i t a l u g e r n i h t i w s i e g a t l o v t u p t u o e h t n e h w e c n a d e p m i h g i h t e s s i c n . d e t c e n n o c y l l a n r e t n i t o n d n g a . c i e h t r o f d n u o r g l a n g i s . n i p s i h t o t t c e p s e r h t i w d e r u s a e m e r a s l e v e l s e g a t l o v l l a d n g p . d n u o r g r e w o p o t d e t c e n n o c y l t c e r i d e b d l u o h s d n a r e v i r d t e f s o m r e w o l r o f d e t a c i d e d s i n i p s i h t . h t a p d e t a l o s i n a h t i w t e f s o m r e w o l e h t f o e c r u o s e h t e t a g l . t u p t u o r e v i r d e t a g r e w o l y b d e r o t i n o m s i n i p s i h t . t e f s o m r e w o l f o e t a g e h t o t n i p s i h t t c e n n o c . f f o d e n r u t s a h t e f s o m r e w o l e h t n e h w e n i m r e t e d o t y r t i u c r i c n o i t c e t o r p h g u o r h t - t o o h s e v i t p a d a e h t c c v p . s r e v i r d e t a g e h t r o f e g a t l o v y l p p u s p a r t s t o o b d n a r e v i r d e t a g r e w o l r o f t n e r r u c s e d i v o r p n i p s i h t . r e t l i f c / r a h t i w t i s s a p y b d n a e c r u o s e g a t l o v v 5 o t n i p s i h t t c e n n o c . r e v i r d e t a g r e p p u r o f t i u c r i c x a m i . e s n e s d n a g n i t t e s d l o h s e r h t t i m i l t n e r r u c r o f t e f s o m e d i s - w o l f o n i a r d o t r o t s i s e r a t c e n n o c r ) n o ( s d ) a 1 1 1 6 p u ( . g n i s n e s . g n i t e s l e v e l n o i t c e t o r p t n e r r u c r e v o p c o e h t t e s o t d n g a o t n i p s i h t m o r f r o t s i s e r a t c e n n o c ) b 1 1 1 6 p u ( . l e v e l e s a h p . e d o n h c t i w s e s a h p e h t f o n i a r d e h t d n a t e f s o m e d i s - h g i h e h t f o e c r u o s e h t o t n i p s i h t t c e n n o c p o r d e g a t l o v e h t r o t i n o m o t d n a , r e v i r d e t a g u e h t r o f k n i s e h t s a d e s u s i n i p s i h t . t e f s o m r e w o l - t o o h s e v i t p a d a e h t y b d e r o t i n o m o s l a s i n i p s i h t . n o i t c e t o r p t n e r r u c r e v o r o f t e f s o m r e w o l e h t s s o r c a . f f o d e n r u t s a h t e f s o m r e p p u e h t n e h w e n i m r e t e d o t y r t i u c r i c n o i t c e t o r p h g u o r h t e t a g u . t u p t u o r e v i r d e t a g r e p p u y b d e r o t i n o m s i n i p s i h t . t e f s o m r e p p u f o e t a g e h t o t n i p s i h t t c e n n o c . f f o d e n r u t s a h t e f s o m r e p p u e h t n e h w e n i m r e t e d o t y r t i u c r i c n o i t c e t o r p h g u o r h t - t o o h s e v i t p a d a e h t t o o b y l p p u s p a r t s t o o b c r o t i c a p a c p a r t s t o o b e h t t c e n n o c . r e v i r d e t a g r e p p u g n i t a o l f e h t r o f t o o b n e e w t e b e g r a h c e h t s e d i v o r p r o t i c a p a c p a r t s t o o b e h t . t i u c r i c p a r t s t o o b a m r o f o t n i p e s a h p e h t d n a n i p t o o b r o f s e u l a v l a c i p y t . t e f s o m r e p p u e h t n o n r u t o tc t o o b c t a h t e r u s n e . f u 7 4 . 0 o t f u 1 . 0 m o r f e g n a r t o o b s i . c i e h t r a e n d e c a l p m s p / n e . n o i t c e l e s e d o m d n a e l b a n e p i h c h t o b f f o s n r u t d n a c i e h t s e l b a s i d v 4 . 0 n a h t r e w o l n i p s i h t g n i l l u p s i h t t e l d n a n o i t a r e p o ) m s p ( e d o m g n i v a s r e w o p r o f c c v o t n i p s i h t e i t . s t e f s o m r e w o l d n a r e p p u . n o i t a r e p o ) m c c f ( e d o m n o i t c u d n o c s u o u n i t n o c e c r o f r o f t a o l f n i p n o t . g n i m m a r g o r p e m i t n o o t ) b 1 1 1 6 p u ( e s a h p r o ) a 1 1 1 6 p u ( n i v o t n i p s i h t m o r f r o t s i s e r a t c e n n o c . t e f s o m r e p p u e h t r o f e m i t - n o e h t t e s t n o 0 1 x 5 8 . 3 = 2 1 - r x n o t v x t u o v ( / n i a 1 1 1 6 p u - ) 5 . 0 - t n o 0 1 x 9 1 = 2 1 - r x n o t v ) 3 / 2 ( [ { x t u o v / ] v m 0 0 1 + n i b 1 1 1 6 p u - s n 0 5 + } d e s o p x e d a p . c i e h t r o f d n u o r g l a n g i s d a p d e s o p x e s i h t . n i p s i h t o t t c e p s e r h t i w d e r u s a e m e r a s l e v e l s e g a t l o v l l a . n o i t c u d n o c t a e h e v i t c e f f e r o f b c p o t d e r e d l o s l l e w e b d l u o h s
upi semiconductor corp., http://www.upi-semi.com rev. f01, file name: up6111a/b-ds-f0101 up6111a/b 6 functional description the up6111a/b is a high performance synchronous-rectified buck controller specifically designed for pol voltage regulation in notebook pc application. the controller operates with 5v bias voltage and converts 2v~26v input voltage to 0.75v~5.5v output voltage. the up6111a/b adopts constant-on-time pwm scheme that features easy-to-use, low external component count, fast transient response and quasi constant frequency operation over the operation range. selectable forced continuous conduction mode (fccm) or power saving mode (psm) enables the flexibility for low noise operation or high efficiency conversion over wide output current range. lossless current sensing by r ds(on) of lower switch achieves programmable over current protection. other features include internal soft start, integrated bootstrap diode and thermal shutdown. uvlo, soft start and pok undervoltage-lockout (uvlo) circuit inhibits switching and reset the protection faults when vcc is below 4v. both lgate and ugate drivers are turned off during uvlo. the soft start of up6111a/b is achieved by internal ramp wave ss with over current limit, results in an internal 1.2ms soft start. the error is an tri-input device, ss or v ref which ever is smaller dominates the behavior of non-inverting input of the error amplifier. on vcc is over its 4v uvlo level and en/psm is floating or high, soft start ss begins to ramp up. the ss signal is created digitally by internal circuit. it takes 1.2ms for the ss to ramp up from 0v to 0.75v. the feedback voltage v fb is regulated to follow the ss during the soft start, resulting in smooth ramp up of the output voltage. the v ref takes over the control after ss is over 0.75v. the ss keeps ramping up to 1.6v, taking about extra 1.5ms. the up6111a/b asserts soft start end when the ss reaches about 1.6v. the pok is an open drain output. the up6111a/b asserts pok high impedance output if the output voltage is within regulation with about 45us time delay after soft start end. if the output voltage is out of 10% of the target value, the pok signal will become low immediately. output voltage setting the output voltage can be adjusted from 0.75v to 5.5v by setting the feedback resistors r1 and r2 (see the typical application circuit). the following equaion is for adjudting the ouput voltage. ? ? ? ? ? ? + = 2 r 1 r 1 v v fb out where v fb is 0.75v (typ.) and keep r2 about 10k ? to choose r1 value. operation mode the up6111a/b supports selectable froced continuous conduction mode (fccm) and power saving mode (psm) operations. if en/psm is grounded, the switching regulator is disabled. if the en/psm pin is connected to 3.3v or 5v, the regulator is enabled with psm selected. if the en/psm pin is floated, it is internally pulled up to 1.9v, and the regulator is enabled with fccm. the up6111a/b features a control loop as adaptive on-time and minimum off-time pulse width modulation (pwm). the upper mosfet is turned on at the beginning of each cycle. it is turned off after the internal one-shot timer expires. another cycle initiates when the feedback voltage v fb is lower than the internal reference voltage v ref and the minimum off-time expires. this regulates the valley of v fb at v ref . for up6111a, the one-shot timer is programmed by a resistor r ton connected from ton pin to v in as: v 5 . 0 v v r pf 85 . 3 t in out ton on ? = where 3.85pf is the internal timing capacitor. for up6111b, the one-shot timer is programmed by a resistor r ton connected from ton pin to phase pin as: ns 50 ) v mv 100 v ) 3 / 2 ( ( r pf 19 t in out ton on + + = where 19pf is the internal timing capacitor, and 50ns represents the turn-off delay time caused by the internal circuit and high-side mosfet. the on-time is determined by v in and v out and is kept fairly constant over a wide input and output voltage range at steady state. these equations provide a good approximation to start with, but the accuracy will be affected by design and selection of high-side mosfet. figure 1 and 2 illustrate the switching frequency vs. r ton relationship for up6111a and up6111b respactively.
upi semiconductor corp., http://www.upi-semi.com rev. f01, file name: up6111a/b-ds-f0101 up6111a/b 7 functional description 0 100 200 300 400 500 600 700 800 900 300 500 700 900 1100 1300 1500 r ton to vin (kohm) switching freqnecy (khz) figure 1. switching frequency vs. r ton. (up6111a) 0 100 200 300 400 500 600 700 100 200 300 400 500 600 r ton to vin (kohm) switching freqnecy (khz) figure 2. switching frequency vs. r ton. (up6111b) power saving mode operation the up6111a/b automatically reduces switching frequency at light load to maintain high efficiency when psm is selected by connecting en/psm to vcc. the frequency reduction is achieved smoothly and without increasing v out ripple or load regulation. as the output current decreases from heavy load condition, the inductor current also decreases and eventually comes to the point that its valley touches zero current at the boundary between continuous and discontinuous conduction modes. the up6111a/b emulates conventional asynchronous buck converter by turning off the lower mosfet when zero inductor current is detected. as the load current decreased, the converter runs in discontinuous conduction mode and it takes a long time to discharge the output capacitor to next on cycle. high/low side gate drivers the lower gate driver is designed to work with high-current and low r ds(on) n-channel mosfets. the lower gate driver is powered by pvcc pin. the driving capability is represented by its internal resistance, that is 1.5 ? for sourcing and 1.0 ? for sinking. a dead time to prevent shoot through is internally generated between upper mosfet off to lower mosfet on and lower mosfet off to upper mosfet on. the upper gate driver is designed to work with high-current and low r ds(on) n-channel mosfets. the upper gate driver work with bootstrap circuit formed by boot and phase pins. the bootstrap diode is integrated to simplified circuit and pcb design. an external schottky diode can be used if the forward drop voltage is critical to achieve best efficiency. the driving capability is represented by its internal resistance, that is 3.0 ? for sourcing and 1.0 ? for sinking. output discharge control (soft stop) the up6111a/b features the soft stop function that discharges the output when the converter is disabled or in a fault condition (uvp, ovp, uvlo or thermal shutdown.) the discharge path is through vout, internal 20 ? mosfet and pgnd pins. the discharge time constant is a function of the output capacitance and resistance of the discharge mosfet. over current protection (up6111a) the up6111a features cycle-by-cycle current limit function. the up6111a monitors the inductor current by lower mosfet r ds(on) when it turns on as shown in figure 3. the up6111a sources a 20ua current source out of imax pin and creates a voltage as: phase imax imax v ua 20 r v + = the high side mosfet will not turn on if the vimax voltage is lower than zero even the voltage loop demands the it to be turned on. the current limit level is calculated as: 2 i r ua 20 r i ripple ) on ( ds imax lim + = where r ds(on) is the on resistance of lower mosfet and i ripple is the inductor current ripple. the output voltage decreases and eventually triggers the under voltage protection if the load continuously demands current larger than the current limit level.
upi semiconductor corp., http://www.upi-semi.com rev. f01, file name: up6111a/b-ds-f0101 up6111a/b 8 imax ocp 20ua up6111a phase r imax figure 3. current limit of up6111a. over current protection (up6111b) the up6111b features cycle-by-cycle current limit function. the up6111b monitors the inductor current by lower mosfet r ds(on) when it turns on as shown in figure 4. the up6111b sources a 10ua current source out of imax pin and creates a voltage as: ua 10 r v imax imax = the imax voltage is added to phase pin voltage for current limit function. the high side mosfet will not turn on if the summation is lower than zero even the voltage loop demands the it to be turned on. the current limit level is calculated as: 2 i r v i ripple ) on ( ds imax lim + = where r ds(on) is the on resistance of lower mosfet and i ripple is the inductor current ripple. the output voltage decreases and eventually triggers the under voltage protection if the load continuously demands current larger than the current limit level. imax ocp phase 10ua up6111b r imax figure 4. current limit of up6111b. functional description over voltage/under voltage protection the up6111a/b monitors feedback voltage v fb for over voltage and under voltage protection. the up6111a/b asserts over voltage protection and turns on the lower mosfet and turns off upper mosfet when the v fb voltage is over 115% of its target value with 30us delay. the ovp protection is latch-off type. it can only be reset by uvlo or toggling the en/psm pin. the up6111a/b asserts under voltage protection and turns off both upper and lower mosfets if the v fb voltage is lower than 70% of its target value with 4us delay. the uvp protection is latch-off type. it can only be reset by uvlo or toggling the en/psm pin. the uvp function is disables during soft cycle. thermal protection the up6111a/b monitors the temperature of itself. if the temperature exceeds typical 150 o c, the up6111a/b will be turned off .this is non-latch protection. it will be recovered once temperature is lower 130 o c.
upi semiconductor corp., http://www.upi-semi.com rev. f01, file name: up6111a/b-ds-f0101 up6111a/b 9 package thermal resistance (note 3) ja wqfn4x4-16l------------------------------------------------------------------------------------------------------------------- -- 37 c/w ja wqfn3x3-16l ------------------------------------------------------------------------------------------------------------------ -- 68 c/w ja vqfn3.5x3.5-14l -------------------------------------------------------------------------------------------------------------- - 42 c/w ja tssop- 14l ------------------------------------------------------------------------------------------------------------------- -- 133 c/w jc wqfn4x4-16l ------------------------------------------------------------------------------------------------------------------ --- 3 c/w jc wqfn3x3-16l ------------------------------------------------------------------------------------------------------------------ --- 5 c/w power dissipation, p d @ t a = 25 c wqfn4x4-16l ------------------------------------------------------------------------------------------------------------------- -------------- 2.70w wqfn3x3-16l ------------------------------------------------------------------------------------------------------------------- -------------- 1.47w vqfn3.5x3.5-14l --------------------------------------------------------------------------------------------------------------- ------------- 2.38w tssop -14l -------------------------------------------------------------------------------------------------------------------- ---------------- 0.75w operating junction temperature range (note 4) ------------------------------------------------------------------------ -40 c to +125 c operating ambient temperature ra nge -------------------------------------------------------------------------------------- -40 c to +85 c power input voltage, v in ----------------------------------------------------------------------------------------------------------- +2v to 26v supply input voltage, pv cc , v cc ----------------------------------------------------------------------------------------------------- +4.5v to 5.5v a bsolute maximum ratin g thermal informatio n recommended operation conditions supply input voltage, vin (note 1) -------------------------------------------------------------------------------------------- -0.3v to +28v vcc & pvcc to gnd ------------------------------------------------------------------------------------------------------------- --------- -0.3v to +6v boot to phase ----------------------------------------------------------------------------------------------------------------- ----------- -0.3v to +6v phase to gnd dc ---------------------------------------------------------------------------------------------------------------------------- ----------- -0.7v to 28v < 200ns ----------------------------------------------------------------------------------------------------------------------- ----------- -8v to 36v boot to gnd dc ------------------------------------------------------------------------------------------------------------------------- -0 .3v to pvcc + 28v < 200ns ----------------------------------------------------------------------------------------------------------------------- --------- -0.3v to 42v ugate to phase dc---------------------------------------------------------------------------------------------------------------- -0.3v to (b ootx - phx +0.3v) <200ns ------------------------------------------------------------------------------------------------------- -5v to (bootx - phx + 0.3v) lgate to gnd dc ------------------------------------------------------------------------------------------------------------------- -0.3v t o + (pvcc + 0.3v) <200ns -------------------------------------------------------------------------------------------------------------- -5v to p vcc + 0.3v other pins to gnd ------------------------------------------------------------------------------------------------------------- -------------- -0.3v to +6v storage temperature range ------------------------------------------------------------------------------------------------------------- -65 o c to +150 o c junction temperature ------------------------------------------------------------------------------------------------------------------------------- ----- 150 o c lead temperature (soldering, 10 sec) ------------------------------------------------------------------------------------------------------------ 260 o c esd rating (note 2) hbm (human body mode) --------------------------------------------------------------------------------------------------------------------- 2kv mm (machine mode) ----------------------------------------------------------------------------------------------------------------------------- 2 00v
upi semiconductor corp., http://www.upi-semi.com rev. f01, file name: up6111a/b-ds-f0101 up6111a/b 10 r e t e m a r a pl o b m y ss n o i t i d n o c t s e tn i mp y tx a mt i n u t u p n i y l p p u s e g n a r e g a t l o v t u p n i r e w o pv n i 2- -6 2v e g n a r e g a t l o v t u p n i y l p p u s v c c , v p c c 5 . 4- -5 . 5v d l o h s e r h t g n i s i r r o p c c vv h t r c c g n i s i r c c v7 . 30 . 43 . 4v s i s e r e t s y h r o p c c vv s y h c c - -3 . 0- -v t n e r r u c y l p p u si q i c c v i + c v p v , b f c c v = m s p / n e . v 8 . 0 =- -0 0 3- -a u t n e r r u c n w o d t u h si n d h s i c c v i + c c v p = m s p / n e , g n i t a o l f = n o t , d n g - -50 1a u b f d n a t u o v v b f y c a r u c c a e g a t l o v n o i t a l u g e rv b f 5 . 2 4 70 5 75 . 7 5 7v m v b f e c n a r e l o t e g a t l o v n o i t a l u g e rv l o t _ b f t a 5 2 = o y c a r u c c a l a i t i n i p a g d n a b , c0 . 1 -- -0 . 1 % t a 0 = o 5 8 o t c o c3 . 1 -- -3 . 1 t a 0 4 - = o 5 8 o t c o c3 . 1 -- -3 . 1 t n e r r u c s a i b b fv b f v 5 7 . 0 =1 . 0 -- -1 . 0a u e g n a r e g a t l o v t u p t u ov t u o 5 7 . 0- -5 . 5v e c n a t s i s e r g n i g r a h c s i d t u o vr t u o d n g = m s p / n e- -0 22 3 ? ) a 1 1 1 6 p u ( t r a t s t f o s l a n r e t n i d n a e m i t n o e m i t n o l a n i m o nt n _ n o v n i v , v 5 1 = t u o r , v 5 2 . 1 = n o t m 1 = ? 4 6 20 3 36 9 3s n e m i t f f o m u m i n i mt ) n i m ( f f o - -0 4 4- -s n e m i t t r a t s t f o s l a n r e t n it s s v o t v 1 > m s p / n e m o r f b f v 1 7 . 0 >9 . 02 . 15 . 1s m ) b 1 1 1 6 p u ( t r a t s t f o s l a n r e t n i d n a e m i t n o e m i t n o l a n i m o nt f _ n o v e s a h p v , v 2 1 = t u o r , v 5 . 2 = n o t = k 0 0 1 ? 4 6 20 3 36 9 3s n e m i t f f o m u m i n i mt ) n i m ( f f o - -0 4 4- -s n e m i t t r a t s t f o s l a n r e t n it s s v o t v 1 > m s p / n e m o r f b f v 1 7 . 0 >9 . 02 . 15 . 1s m s r e v i r d e t a g g n i c r u o s r e v i r d e t a g ur c r s _ h i c r s _ h a m 0 5 1 =- -0 . 30 . 6 ? g n i k n i s r e v i r d e t a g ur k n s _ h i k n s _ h a m 0 5 1 =- -0 . 10 . 2 ? g n i c r u o s r e v i r d e t a g lr c r s _ l i c r s _ l a m 0 5 1 =- -5 . 10 . 3 ? g n i k n i s r e v i r d e t a g lr k n s _ l i k n s _ l a m 0 5 1 =- -0 . 10 . 2 ? e m i t d a e dn g i s e d y b- -0 2- -s n e d o i d p a r t s t o o b e g a t l o v d r a w r o fv f _ t s b i f a m 0 1 =7 . 08 . 09 . 0v t n e r r u c e g a k a e l e s r e v e ri k l _ t s b v t o o b v 8 2 =- -1 . 01a u electrical characteristics (pv cc = v cc = 5.0v, t a = 25 o c, unless otherwise specified)
upi semiconductor corp., http://www.upi-semi.com rev. f01, file name: up6111a/b-ds-f0101 up6111a/b 11 note 1. stresses listed as the above ? absolute maximum ratings ? may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. devices are esd sensitive. handling precaution recommended. note 3. ja is measured in the natural convection at t a = 25 c on a low effective thermal conductivity test board of jedec 51-3 thermal measurement standard. note 4. the device is not guaranteed to function outside its operating conditions. r e t e m a r a pl o b m y ss n o i t i d n o c t s e tn i mp y tx a mt i n u e s n e s t n e r r u c t n e r r u c e c r u o s x a m ii x a m i a 1 1 1 6 p u8 10 22 2a u b 1 1 1 6 p u90 11 1a u t e s f f o r o t a r a p m o c p c ov s f o _ c o 0 1 -00 1v m t e s f f o r o t a r a p m o c p c o e v i t a g e nv s f o _ c o y l n o b 1 1 1 6 p u r o f5 . 9 -5 . 05 . 0 1v m t e s f f o r o t a r a p m o c g n i s s o r c o r e zv f o _ c z 5 . 9 -5 . 05 . 0 1v m l e v e l n o i t c e t o r p d n a c i g o l w o l c i g o l m s p / n e - -- -7 . 0v h g i h c i g o l m s p / n e 9 . 2- -- -v l e v e l g n i t a o l f m s p / n e 6 . 19 . 12 . 2v t n e r r u c e c r u o s m s p / n ei m s p / n e d n g = m s p / n e- -1- -a u r e w o l m o r f d l o h s e r h t k o r e w o pv b f v f o e g a t n e c r e p , g n i s i r f e r 7 80 93 9% s i s e r e t s y h w o l k o r e w o pv b f v f o e g a t n e c r e p , g n i l l a f f e r - -3 -- -% r e h g i h m o f d l o h s e r h t k o r e w o pv b f v f o e g a t n e c r e p , g n i l l a f f e r 7 0 10 1 13 1 1% s i s e r e t s y h h g i h k o r e w o pv b f v f o e g a t n e c r e p , g n i s i r f e r - -3- -% t n e r r u c g n i k n i s k o r e w o pi k o p v k o p . v 5 . 0 =2- -- -a m e m i t y a l e d k o r e w o p - -5 4- -s u l e v e l p i r t e g a t l o v r e v ov p v o v f o e g a t n e c r e p f e r 1 1 15 1 19 1 1% e m i t y a l e d e g a t l o v r e v o - -0 3- -s u l e v e l p i r t e g a t l o v r e d n uv p v u v f o e g a t n e c r e p f e r 5 60 75 7% e m i t y a l e d e g a t l o v r e d n u - -4- -s u l e v e l e r u t a r e p m e t p t ot h t t o - -0 5 1- - o c s i s e r e t s y h e r u t a r e p m e t p t ot s y h t o - -0 2- - o c electrical characteristics
upi semiconductor corp., http://www.upi-semi.com rev. f01, file name: up6111a/b-ds-f0101 up6111a/b 12 v out (50mv/div) i l (5a/div) i out (5a/div) phase (10v/div) v out (50mv/div) i l (5a/div) i out (5a/div) phase (10v/div) en (2v/div) phase (10v/div) pok (5v/div) v out (0.5v/div) en (1v/div) phase (5v/div) pok (2v/div) v out (0.5v/div) en (2v/div) phase (5v/div) pok (2v/div) v out (0.5v/div) typical operation characteristics phase (5v/div) pok (2v/div) v out (0.5v/div) v cc (2v/div) load transient response time: 5us v in = 10v, v out = 1.5v, i out = 0 to 8a transient, fccm load transient response time: 5us v in = 10v, v out = 1.5v, i out = 0 to 8a transient, psm power on waveforms time: 1ms/div v in = 7.0v, v cc = 5v turn off @ fccm time: 2.5us/div v in = 12v, v cc = 5v, i out = 2a turn on waveforms @ psm time: 2.5ms/div v in = 12v, v cc = 5v turn on waveforms @ fccm time: 500us/div v in = 12v, v cc = 5v
upi semiconductor corp., http://www.upi-semi.com rev. f01, file name: up6111a/b-ds-f0101 up6111a/b 13 200 220 240 260 280 300 -50 0 50 100 150 v out (50mv/div) i l (5a/div) i out (5a/div) phase (10v/div) load transient response time: 5us/div v in = 10v, v out = 1.5v, i out = 8 to 0a transient, psm v out (50mv/div) i l (5a/div) i out (5a/div) phase (10v/div) load transient response time: 5us/div v in = 10v, v out = 1.5v, i out = 8 to 0a transient, fccm v out (50mv/div) i l (5a/div) en/psm (5v/div) phase (10v/div) fccm topsm transition time: 5us v in = 10v, v out = 1.5v v out (50mv/div) i l (5a/div) en/psm (5v/div) phase (10v/div) psm to fccm transition time: 5us v in = 10v, v out = 1.5v typical operation characteristics frequency vs. temperature temperature ( o c) (up6111a) frequency (khz) 200 220 240 260 280 300 -50 0 50 100 150 frequency vs. temperature temperature ( o c) (up6111b) frequency (khz)
upi semiconductor corp., http://www.upi-semi.com rev. f01, file name: up6111a/b-ds-f0101 up6111a/b 14 -1.5 -1.3 -1.1 -0.9 -0.7 -0.5 -0.3 -0.1 0.1 0.3 0.5 -50 0 50 100 150 10 12 14 16 18 20 22 24 26 28 30 -50 0 50 100 150 4 6 8 10 12 14 16 18 -50 0 50 100 150 0.85 0.87 0.89 0.91 0.93 0.95 0.97 0.99 4 9 14 19 24 40 50 60 70 80 90 100 110 120 130 -50 0 50 100 150 uvp ovp typical operation characteristics imax current vs. temperature temperature ( o c) (up6111b) imax current (ua) imax current vs. temperature temperature ( o c) (up6111a) imax current (ua) ovp/uvp threshold vs. temperature temperature ( o c) ovp/uvp threshold level (%) enable/disable threshold voltage vs. v in input voltage(v) enable/disable threshold voltage (v) v fb vs. temperature temperature ( o c) v fb (%) 0 100 200 300 400 500 600 700 800 -50 0 50 100 150 supply current vs. temperature temperature ( o c) supply current (ua)
upi semiconductor corp., http://www.upi-semi.com rev. f01, file name: up6111a/b-ds-f0101 up6111a/b 15 150 175 200 225 250 275 300 325 350 0 5 10 15 20 25 typical operation characteristics switchung frequency vs. input voltage input voltage(v) (up6111a) switching frequency (khz) switching frequency vs. input voltage input voltage (v) (up6111b) switching frequency (khz) 240 245 250 255 260 265 270 275 280 285 290 0 5 10 15 20 25 0 50 100 150 200 250 300 350 400 0.001 0.01 0.1 1 10 pwm psm frequency vs. output current output current (ma) frequency (khz) 1.43 1.45 1.47 1.49 1.51 1.53 5 10152025 1.45 1.46 1.47 1.48 1.49 1.5 1.51 1.52 1.53 1.54 1.55 0 5 10 15 20 line regulation input voltage (v) output voltage (v) load regulation output current (a) ouput voltage (v)
upi semiconductor corp., http://www.upi-semi.com rev. f01, file name: up6111a/b-ds-f0101 up6111a/b 16 a pplication information component selection external component selection is primarily determined by the maximum load current and begins with the selection of power mosfet switches. the up6111a/b uses the on- resistance of the lower switch for determining the inductor current. the desired amount of ripple current and operating frequency largely determines the inductor value. finally, c in is selected for its ability to handle the large rms current into the converter and c out is chosen with enough esr to meet the stability, output voltage ripple and transient specification. power mosfet selection the up6111a/b requires two external n-channel power mosfets for upper (controlled) and lower (synchronous) switches. important parameters for the power mosfets are the breakdown voltage v (br)dss , on-resistance r ds(on) , reverse transfer capacitance c rss , maximum current i ds(max) , gate supply requirements, and thermal management requirements. the gate drive voltage is powered by pvcc pin that receives 4.5v~5.5v supply voltage. when operating with a 5v power supply for pvcc, a wide variety of nmosfets can be used. .since the lower mosfet is used as the current sensing element, particular attention must be paid to its on- resistance. look for r ds(on) ratings at lowest gate driving voltage. special cautions should be exercised on the lower switch exhibiting very low threshold voltage v gs(th) . the shoot- through protection present aboard the up6111a/b may be circumvented by these mosfets if they have large parasitic impedances and/or capacitances that would inhibit the gate of the mosfet from being discharged below its threshold level before the complementary mosfet is turned on. also avoid mosfets with excessive switching times; the circuitry is expecting transitions to occur in under 50 ns or so. in high-current applications, the mosfet power dissipation, package selection and heatsink are the dominant design factors. the power dissipation includes two loss components; conduction loss and switching loss. the conduction losses are the largest component of power dissipation for both the upper and the lower mosfets. these losses are distributed between the two mosfets according to duty cycle. since the up6111a/b is operating in continuous conduction mode, the duty cycles for the mosfets are: in out up v v d = ; in out in lo v v v d ? = the resulting power dissipation in the mosfets at maximum output current are: osc sw in out up ) on ( ds 2 out up f t v i 5 . 0 d r i p + = lo ) on ( ds 2 out lo d r i p = where t sw is the combined switch on and off time. both mosfets have i 2 r losses and the top mosfet includes an additional term for switching losses, which are largest at high input voltages. the bottom mosfet losses are greatest when the bottom duty cycle is near 100%, during a short-circuit or at high input voltage. these equations assume linear voltage current transitions and do not adequately model power loss due the reverse-recovery of the lower mosfet?s body diode. ensure that both mosfets are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. a separate heatsink may be necessary depending upon mosfet power, package type, ambient temperature and air flow. the gate-charge losses are dissipated by the up6111a/b and don?t heat the mosfets. however, large gate charge increases the switching interval, t sw that increases the mosfet switching losses. the gate-charge losses are calculated as: osc rss in lo _ iss up _ iss cc cc g f ) c v ) c c ( v ( v p + + = where c iss_up is the input capacitance of the upper mosfet, c iss_lo is the input capacitance of the lower mosfet, and c rss_up is the reverse transfer capacitance of the upper mosfet. make sure that the gate-charge loss will not cause over temperature at up6111a/b, especially with large gate capacitance and high supply voltage. output inductor selection output inductor is usually selected by considering inductance, rated current value, size requirement and dc resistance (dcr). given the desired input and output voltages, the inductor value and operating frequency determine the ripple current: ) v v 1 ( v l f 1 i in out out out osc l ? = ? lower ripple current reduces core losses in the inductor, esr losses in the output capacitors and output voltage ripple. highest efficiency operation is obtained at low frequency with small ripple current. however, achieving this requires a large inductor. there is a trade off between
upi semiconductor corp., http://www.upi-semi.com rev. f01, file name: up6111a/b-ds-f0101 up6111a/b 17 a pplication information component size, efficiency and operating frequency. a reasonable starting point is to choose a ripple current that is about 40% of i out(max) . there is another trade off between output ripple current/ voltage and response time to a transient load. increasing the value of inductance reduces the output ripple current and voltage. however, the large inductance values reduce the converter response time to a load transient. maximum current ratings of the inductor are generally specified in two methods: permissible dc current and saturation current. permissible dc current is the allowable dc current that causes 40 o c temperature raise. the saturation current is the allowable current that causes 10% inductance loss. make sure that the inductor will not saturate over the operation conditions including temperature range, input voltage range, and maximum output current. the size requirements refer to the area and height requirement for a particular design. for better efficiency, choose a low dc resistance inductor. dcr is usually inversely proportional to size. different core materials and shapes will change the size/ current and price/current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy materials are small and don?t radi ate much energy, but generally cost more than powdered iron core inductors with similar electrical characteristics. the choice of which style inductor to use often depends more on the price vs. size requirements and any radiated field/emi requirements. input capacitor selection the synchronous-rectified buck converter draws pulsed current with sharp edges from the input capacitor resulting in ripples and spikes at the input supply voltage. use a mix of input bypass capacitors to control the voltage overshoot across the mosfets. use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time upper mosfet turns on. place the small ceramic capacitors physically close to the mosfets and between the drain of upper moset and the source of lower mosfet to avoid the stray inductance along the connection trace. the important parameters for the bulk input capacitor are the voltage rating and the rms current rating. for reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest rms current required by the circuit. the capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. the rms current rating requirement for the input capacitor of a buck converter is calculated as: in out in out ) max ( out ) rms ( in v ) v v ( v i i ? = this formula has a maximum at v in = 2v out , where i in(rms) = i out(rms) /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. note that the capacitor manufa cturer?s ri pple current ratings are often based on 2000 hours of life. this makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. always consult the manufacturer if there is any question. for a through-hole design, several electrolytic capacitors may be needed. for surface mount designs, solid tantalum capacitors can also be used, but caution must be exercised with regard to the capacitor surge current rating. these capacitors must be capable of handling the surge-current at power-up. some capacitor series available from reputable manufacturers are surge current tested. output capacitor selection an output capacitor is required to filter the output and supply the load transient current. the selection of c out is primarily determined by the esr required to minimize voltage ripple and load step transients. the output ripple ? v out is approximately bounded by: ) c f 8 1 esr ( i v out osc l out + ? ? since ? il increases with input voltage, the output ripple is highest at maximum input voltage. typically, once the esr requirement is satisfied, the capacitance is adequate for filtering and has the necessary rms current rating. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. special polymer capacitors offer very low esr but have lower capacitance density than other types. the load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. these requirements are generally met with a mix of capacitors and careful layout. modern components and loads are capable of producing transient load rates above 1a/ns. high frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. the bulk filter capacitor values are generally determined by the esr (effective series resistance) and voltage rating requirements rather than actual capacitance requirements.
upi semiconductor corp., http://www.upi-semi.com rev. f01, file name: up6111a/b-ds-f0101 up6111a/b 18 a pplication information high frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. consult with the manufacturer of the load on specific decoupling requirements. use only specialized low-esr capacitors intended for switching-regulator applications for the bulk capacitors. the bulk capacitor?s esr will determine the output ri pple voltage and the initial voltage drop after a high slew-rate transient. an aluminum electrolytic capa citor?s esr value is related to the case size with lower esr available in larger case sizes. however, the equivalent series inductance (esl) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. unfortunately, esl is not a specified parameter. work with your capacitor supplier and measure the capa citor?s impedance with frequency to select a suitable component. in most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. bootstrap capacitor selection an external bootstrap capacitor c boot connected to the boot pin supplies the gate drive voltage for the upper mosfet. this capacitor is charged through the internal diode when the phase node is low. when the upper mosfet turns on, the phase node rises to v in and the boot pin rises to approximately v in + pv cc . the boot capacitor needs to store about 100 times the gate charge required by the upper mosfet. in most applications 0.1 f to 0.47 f, x5r or x7r dielectric capacitor is adequate. checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to ? i load x (esr), where esr is the effective series resistance of c out . ? i load also begins to charge or discharge c out generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. pcb layout considerations high speed switching and relatively large peak currents in a synchronous-rectified buck converter make the pcb layout a very important part of design. fast current switching from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. the voltage spikes can degrade efficiency and radiate noise that result in overvoltage stress on devices. careful component placement and printed circuit design minimize the voltage spikes induced in the converter. follow the layout guidelines for optimal performance of up6111a/b. 1 place the power components on the top side of pcb, including input/output capacitors, output inductors and power mosfets. 2 use a dedicated grounding plane and use vias to ground all critical components to this layer. the ground plane layer should not have any traces and it should be as close as possible to the layer with power mosfets. use an immediate via to connect the components to ground plane including gnd of up6111. use several bigger vias for power components. 3 apply another solid layer as a power plane and cut this plane into smaller islands of common voltage levels. the power plane should support the input power and output power nodes to maintain good voltage filtering and to keep power losses low. also, for higher currents, it is recommended to use a multilayer board to help with heat sinking power components. 4 the phase node is subject to very high dv/dt voltages. stray capacitance between this island and the surrounding circuitry tend to induce current spike and capacitive noise coupling. keep the sensitive circuit away from the phase node and keep the pcb area small to limit the capacitive coupling. however, the pcb area should be kept moderate since it also acts as main heat convection path of the lower mosfet. 5 up6111 sources/sinks impulse current with 2a peak to turn on/off the upper and lower mosfets. the connecting trance between the controller and gate/ source of the mosfet should be wide and short to minimize the parasitic inductance along the traces. 6 flood all unused areas on all layers with copper. flooding with copper will reduce the temperature rise of power component. 7 provide local vcc decoupling between vcc and gndpins. locate the capacitor, c boot as close as practical to the boot and phase pins.
upi semiconductor corp., http://www.upi-semi.com rev. f01, file name: up6111a/b-ds-f0101 up6111a/b 19 note 1.package outline unit description: bsc: basic. represents theoretical exact dimension or dimension target min: minimum dimension specified. max: maximum dimension specified. ref: reference. represents dimension for reference use only. this value is not a device specification. typ. typical. provided as a general value. this value is not a device specification. 2.dimensions in millimeters. 3.drawing not to scale. 4.these dimensions do not include mold flash or protrusions. mold flash or protrusions shell not exceed 0.15mm. package informatio n wqfn4x4-16 package 3.90 - 4.10 pin 1 mark bottom view - exposed pad 2.50 - 2.80 0.25 - 0.35 2.50 - 2.80 0.30 - 0.50 4.55- 4.65 3.90 - 4.10 0.00 - 0.05 0.80 max 0.20 bsc recommended solder pad pitch and dimensions 0.25 - 0.35
upi semiconductor corp., http://www.upi-semi.com rev. f01, file name: up6111a/b-ds-f0101 up6111a/b 20 note 1.package outline unit description: bsc: basic. represents theoretical exact dimension or dimension target min: minimum dimension specified. max: maximum dimension specified. ref: reference. represents dimension for reference use only. this value is not a device specification. typ. typical. provided as a general value. this value is not a device specification. 2.dimensions in millimeters. 3.drawing not to scale. 4.these dimensions do not include mold flash or protrusions. mold flash or protrusions shell not exceed 0.15mm. package informatio n wqfn3x3-16l package 2.90 - 3.10 pin 1 mark bottom view - exposed pad 1.55 -1.65 1.45-1.75 0.18 - 0.30 1.45 - 1.75 0.35 - 0.45 1.95 - 2.05 3.55 - 3.65 2.90 - 3.10 0.00 - 0.05 0.80 max 0.20 bsc recommended solder pad pitch and dimensions 0.18 - 0.30
upi semiconductor corp., http://www.upi-semi.com rev. f01, file name: up6111a/b-ds-f0101 up6111a/b 21 vqfn3.5x3.5-14l package package informatio n note 1.package outline unit description: bsc: basic. represents theoretical exact dimension or dimension target min: minimum dimension specified. max: maximum dimension specified. ref: reference. represents dimension for reference use only. this value is not a device specification. typ. typical. provided as a general value. this value is not a device specification. 2.dimensions in millimeters. 3.drawing not to scale. 4.these dimensions do not include mold flash or protrusions. mold flash or protrusions shell not exceed 0.15mm. 3.35 - 3.65 pin 1 mark bottom view - exposed pad 1.90 -2.15 1.90 - 2.15 0.18 - 0.30 1.90 - 2.15 0.30 - 0.50 2.55 - 2.65 3.95 - 4.05 3.35 - 3.65 0.00 - 0.05 1.00 max 0.20 bsc recommended solder pad pitch and dimensions 0.18 - 0.30 1.50 bsc 1.50 bsc
upi semiconductor corp., http://www.upi-semi.com rev. f01, file name: up6111a/b-ds-f0101 up6111a/b 22 package informatio n tssop-14l package note 1.package outline unit description: bsc: basic. represents theoretical exact dimension or dimension target min: minimum dimension specified. max: maximum dimension specified. ref: reference. represents dimension for reference use only. this value is not a device specification. typ. typical. provided as a general value. this value is not a device specification. 2.dimensions in millimeters. 3.drawing not to scale. 4.these dimensions do not include mold flash or protrusions. mold flash or protrusions shell not exceed 0.15mm. 4.90 - 5.10 6.20 - 6.60 5.00 bsc 0.05 - 0.15 0.19 - 0.30 0.50 - 0.75 0.25 bsc 7.00 min 0.35 ref 0.65 ref 4.30 - 4.50 6.00 ref 5.00 min recommended solder pad layout 1.20 max 0.80 - 1.05 0.19 - 0.30 0.65 bsc

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